pin function pin function 1 +3.2v ref . out 40 no connection 2 unipolar 39 no connection 3 analog input 38 +5v analog suppl y 4 analog ground 37 ?5v suppl y 5 offset adjust 36 analog ground 6 gain adjust 35 comp . bits 7 digit al gr ound 34 output enable 8 fifo/dir 33 o verflo w 9 fifo read 32 eoc 10 fst a t1 31 +5v digit al suppl y 11 fst a t2 30 digit al gr ound 12 st ar t conver t 29 bit 1 (msb) 13 bit 16 (lsb) 28 bit 1 (msb) 14 bit 15 27 bit 2 15 bit 14 26 bit 3 16 bit 13 25 bit 4 17 bit 12 24 bit 5 18 bit 11 23 bit 6 19 bit 10 22 bit 7 20 bit 9 21 bit 8 fea tures 16-bit resolution 1mhz sampling rate functionally complete no missing codes over full military temperature range edge-triggered 5v supplies, 1.85 watts small, 40-pin, ceramic tdip 87db snr, ?89db thd ideal for both time and frequency-domain applications 16-bit, 1mhz sampling a/d converters ? ? innov a tion and ex cellence general description the low-cost ads-931 is a 16-bit, 1mhz sampling a/d converter. this device accurately samples full-scale input signals up to nyquist frequencies with no missing codes. the dynamic performance of the ads-931 has been optimized to achieve a signal-to-noise ratio (snr) of 87db and a total harmonic distortion (thd) of ?89db. packaged in a 40-pin tdip, the functionally complete ads-931 contains a fast-settling sample-hold amplifier, a subranging (two- pass) a/d converter, an internal reference, timing/control logic, and error-correction circuitry. digital input and output levels are ttl. the ads-931 only requires the rising edge of the start convert pulse to operate. requiring only 5v supplies, the ads-931 dissipates 1.85 watts. the device is offered with a bipolar (2.75v) analog input range or a unipolar (0 to ? 5.5v) input range. models are available for use in either commercial (0 to +70c) or military (?55 to +125c) operating temperature ranges. a proprietary, auto-calibrating, error-correcting circuit enables the device to achieve specified performance over the full military temperature range. typical applications include medical imaging, radar, sonar, communications and instrumentation. input/output connections ads-931 datel, inc., mansfield, ma 02048 ( usa ) tel: (508)339-3000, (800)233-2756 fax: (508)339-6356 e-mail:sales@datel.com internet: www.datel.com figure 1. ads-931 functional block diagram 3 - s t a t e o u t p u t r e g i s t e r 29 bit 1 (msb) 28 bit 1 (msb) 27 bit 2 26 bit 3 25 bit 4 24 bit 5 23 bit 6 22 bit 7 21 bit 8 20 bit 9 19 bit 10 18 bit 11 17 bit 12 16 bit 13 15 bit 14 14 bit 15 13 bit 16 (lsb) timing and control logic gain adjust 6 +3.2v ref. out 1 offset adjust 5 eoc 32 analog ground 4, 36 digital ground 7, 30 +5v digital supply 31 ?5v supply 37 +5v analog supply 38 no connection 39, 40 c u s t o m g a t e a r r a y power and grounding 2 - p a s s a n a l o g - t o - d i g i t a l c o n v e r t e r s/h gain adjust ckt. offset adjust ckt. precision +3.2v reference analog input 3 start convert 12 comp. bits 35 10 fstat1 11 fstat2 8 fifo/dir 9 fifo/read 34 output enable 33 overflow unipolar 2 offset adjust 5
ads-931 ? ? 2 +25c 0 to +70c ?55 to +125c analog inputs min. typ. max. min. typ. max. min. typ. max. units input voltage ranges unipolar ? 0 to ?5.5 ? ? 0 to ?5.5 ? ? 0 to ?5.5 ? volts bipolar ? 2.75 ? ? 2.75 ? ? 2.75 ? volts input resistance (pin 3) ? 685 ? ? 685 ? ? 685 ? w input resistance (pin 2) ? 400 ? ? 426 ? ? 426 ? w input capacitance ? 10 15 ? 10 15 ? 10 15 pf digital inputs logic levels logic "1" +2.0 ? ? +2.0 ? ? +2.0 ? ? volts logic "0" ? ? +0.8 ? ? +0.8 ? ? +0.8 volts logic loading "1" ? ? +20 ? ? +20 ? ? +20 a logic loading "0" ? ? ?20 ? ? ?20 ? ? ?20 a start convert positive pulse width a 40 100 ? 40 100 ? 40 100 ? ns static performance resolution ? 16 ? ? 16 ? ? 16 ? bits integral nonlinearity ? 1 ? ? 1.5 ? ? 2 ? lsb differential nonlinearity (f in = 10khz) ? 0.95 0.5 +1.0 ? 0.95 0.5 +1.0 ? 0.95 0.5 +1.5 lsb full scale absolute accuracy ? 0.1 0.3 ? 0.15 0.5 ? 0.5 0.8 %fsr bipolar zero error (tech note 2) ? 0.1 0.2 ? 0.2 0.4 ? 0.5 0.9 %fsr bipolar offset error (tech note 2) ? 0.1 0.3 ? 0.2 0.5 ? 0.4 0.9 %fsr gain error (tech note 2) ? 0.1 0.3 ? 0.15 0.5 ? 0.5 0.9 % no missing codes (f in = 10khz) 16 ? ? 16 ? ? 16 ? ? bits dynamic performance peak harmonics (?0.5db) dc to 250khz ? ?91 ? 85 ? ?91 ? 85 ? ? 90 ? 83 db 250khz to 500khz ? ?91 ? 85 ? ?91 ? 85 ? ? 90 ? 83 db total harmonic distortion (?0.5db) dc to 250khz ? ? 89 ? 83 ? ? 89 ? 83 ? ? 87 ? 81 db 250khz to 500khz ? ? 87 ? 80 ? ? 87 ? 80 ? ? 85 ? 79 db signal-to-noise ratio (w/o distortion, ?0.5db) dc to 250khz 84 87 ? 84 87 ? 82 86 ? db 250khz to 500khz 83 86 ? 83 86 ? 80 84 ? db signal-to-noise ratio ? (& distortion, ?0.5db) dc to 250khz 80 85 ? 80 85 ? 77 83 ? db 250khz to 500mhz 79 84 ? 79 84 ? 76 82 ? db noise ? 82 ? ? 82 ? ? 82 ? vrms two-tone intermodulation distortion (f in = 98khz, 240khz, f s = 1mhz, ?0.5db) ? ? 89 ? ? ? 89 ? ? ? 89 ? db input bandwidth (?3db) small signal (?20db input) ? 4.8 ? ? 4.8 ? ? 4.8 ? mhz large signal (?0.5db input) ? 4.1 ? ? 4.1 ? ? 4.1 ? mhz feedthrough rejection (f in = 480khz) ? 90 ? ? 90 ? ? 90 ? db slew rate ? 51 ? ? 51 ? ? 51 ? v/s aperture delay time ? +8 ? ? +8 ? ? +8 ? ns aperture uncertainty ? 5 ? ? 5 ? ? 5 ? ps rms s/h acquisition time ( to 0.001%fsr, 5.5v step) 700 725 ? 700 725 ? 700 725 ? ns p arameters min. typ . max. units operating temp. range, case ads-931mc 0 ? +70 c ADS-931MM ? 55 ? +125 c thermal impedance q jc ? 4 ? c/watt q ca ? 18 ? c/watt storage temperature range ? 65 ? +150 c package type 40-pin, metal-sealed, ceramic tdip weight 0.56 ounces (16 grams) absolute maximum ra tings p arameters limits units +5v supply (pins 31, 38) 0 to +6 volts ?5v supply (pin 37) 0 to ? 6 volts digital inputs (pins 8, 9, 12, 34, 35) ? 0.3 to +v dd +0.3 volts analog input (pin 3) volts bipolar 5 volts unipolar ?10 to +5 volts lead temperature (10 seconds) +300 c physical/envir onment al functional specifica tions (t a = +25c, v cc = 5v, +v dd = +5v, 1mhz sampling rate, and a minimum 3 minute warm-up unless otherwise specified.)
ads-931 ? ? 3 +25c 0 t o +70c ?55 t o +125c dynamic performance (cont.) min. typ. max. min. typ. max. min. typ. max. units overvoltage recovery time ? ? ? 1000 ? ? 1000 ? ? 1000 ns a/d conversion rate 1 ? ? 1 ? ? 1 ? ? mhz footnotes: ? effective bits is equal to: all power supplies must be on before applying a start convert pulse. all supplies and the clock (start convert) must be present during warm-up periods. the device must be continuously converting during this time. there is a slight degradation in performance when operating the device in the unipolar mode. when comp. bits (pin 35) is low, logic loading "0" will be ?350a. a a 1mhz clock with a positive pulse width is used for all production testing. see timing diagram for more details. 40ns < start pulse < 175ns or 280ns < start pulse < 460ns 6.02 (snr + distortion) ? 1.76 + 20 log full scale amplitude actual input amplitude ? this is the time required before the a/d output data is valid once the analog input is back within the specified range. this time is only guaranteed if the input does not exceed 4.75v (bipolar) or +2 to ?7.5v (unipolar). ? the minimum supply voltages of +4.9v and ?4.9v for v dd are required for ?55c operation only. the minimum limits are +4.75v and ?4.75v when operating at +125c. technical no tes 1. obtaining fully specified performance from the ads-931 requires careful attention to pc-card layout and power supply decoupling. the device's analog and digital ground systems are connected to each other internally. for optimal perfor- mance, tie all ground pins (4, 7, 30 and 36) directly to a large analog ground plane beneath the package. bypass all power supplies and the +3.2v reference output to ground with 4.7f tantalum capacitors in parallel with 0.1f ceramic capacitors. locate the bypass capacitors as close to the unit as possible. 2. the ads-931 achieves its specified accuracies without the need for external calibration. if required, the device's small initial offset and gain errors can be reduced to zero using the adjustment circuitry shown in figure 2. when using this circuitry, or any similar offset and gain calibration hardware, make adjustments following warm-up. to avoid interaction, always adjust offset before gain. tie pins 5 and 6 to analog ground (pin 4) if not using offset and gain adjust circuits. 3. pin 35 (comp. bits) is used to select the digital output coding format of the ads-931 (see tables 2a and 2b). when this pin has a ttl logic "0" applied, it complements the ads- 931?s b1-b16 & b1 outputs. pin 35 is ttl compatible and can be directly driven with digital logic in applications requiring dynamic control over its function. there is an internal pull-up resistor on pin 35 allowing it to be either connected to +5v or left open when a logic "1" is required. 4. to enable the three-state outputs, connect output enable (pin 34) to a logic "0" (low). to disable, connect pin 34 to a logic "1" (high). 5. applying a start convert pulse while a conversion is in progress (eoc = logic "1") will initiate a new and probably inaccurate conversion cycle. data from both the interrupted and subsequent conversions will be invalid. analog output internal reference voltage 3.15 +3.2 3.25 3.15 +3.2 3.25 3.15 +3.2 3.25 volts drift ? 30 ? ? 30 ? ? 30 ? ppm/c external current ? 5 ? ? 5 ? ? 5 ? ma digital outputs logic levels logic "1" +2.4 ? ? +2.4 ? ? +2.4 ? ? volts logic "0" ? ? +0.4 ? ? +0.4 ? ? +0.4 volts logic loading "1" ? ? ? 4 ? ? ? 4 ? ? ? 4 ma logic loading "0" ? ? +4 ? ? +4 ? ? +4 ma delay, falling edge of enable to output data valid ? ? 20 ? ? 20 ? ? 20 ns output coding straight binary, complementary binary, complementary offset binary, complementary two's complement, offset binary, two's complement power requirements power supply ranges ? +5v supply +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 +4.9 +5.0 +5.25 volts ?5v supply ? 4.75 ?5.0 ?5.25 ? 4.75 ?5.0 ?5.25 ? 4.9 ?5.0 ?5.25 volts power supply currents +5v supply ? +225 260 ? +225 260 ? +225 260 ma ?5v supply ?140 ?135 ? ?140 ?135 ? ?140 ?135 ? ma power dissipation ? 1.85 2.0 ? 1.85 2.0 ? 1.85 2.0 watts power supply rejection ? ? 0.07 ? ? 0.07 ? ? 0.07 %fsr/%v
ads-931 ? ? 4 delay pin transition min. typ. max. units direct mode to fifo enabled 8 ? 10 20 ns fifo enabled to direct mode 8 ? 10 20 ns fifo read to output data valid 9 ? ? 40 ns fifo read to status update when changing from ads-931 ? ? 5 for operation without gain adjustment. zero/offset adjust procedure 1. apply a train of pulses to the start convert input (pin 12) so that the converter is continuously converting. 2. for unipolar or bipolar zero/offset adjust, apply ?42v to the analog input (pin 3). 3. for bipolar inputs, adjust the offset potentiometer until the code flickers between 1000 0000 0000 0000 and 0111 1111 1111 1111 with pin 35 tied high (complementary offset binary) or between 0111 1111 1111 1111 and 1000 0000 0000 0000 with pin 35 tied low (offset binary). for unipolar inputs, adjust the offset potentiometers until all output bits are 0's and the lsb flickers between 0 and 1 with pin 35 tied high (straight binary) or until all bits are 1's and the lsb flickers between 0 and 1 with pin 35 tied low (complementary binary). 4. two's complement coding requires using bit 1 (msb) (pin 29). with pin 35 tied low, adjust the trimpot until the output code flickers between all 0?s and all 1?s. gain adjust procedure 1. apply +2.749874v to the analog input (pin 3). 2. for bipolar inputs, adjust the gain potentiometer until all output bits are 0?s and the lsb flickers between a 1 and 0 with pin 35 tied high (complementary offset binary) or until all output bits are 1?s and the lsb flickers between a 1 and 0 with pin 35 tied low (offset binary). 3. two's complement coding requires using bit 1 (msb) (pin 29). with pin 35 tied low, adjust the gain trimpot until the output code flickers equally between 0111 1111 1111 1111 and 0111 1111 1111 1110. calibra tion pr ocedure connect the converter per figure 2. any offset/gain calibration procedures should not be implemented until the device is fully warmed up. to avoid interaction, adjust offset before gain. the ranges of adjustment for the circuits in figure 2 are guaranteed to compensate for the ads-931?s initial accuracy errors and may not be able to compensate for additional system errors. a/d converters are calibrated by positioning their digital outputs exactly on the transition point between two adjacent digital output codes. this is accomplished by connecting led's to the digital outputs and performing adjustments until certain led's "flicker" equally between on and off. other approaches employ digital comparators or microcontrollers to detect when the outputs change from one code to the next. for the ads-931, offset adjusting is normally accomplished when the analog input is 0 minus ? lsb (?42v). see table 2b for the proper bipolar output coding. gain adjusting is accomplished when the analog input is at nominal full scale minus 1? lsb's (+2.749874v). note: connect pin 5 to analog ground (pin 4) for operation without zero/offset adjustment. connect pin 6 to pin 4 figure 2. bipolar connection diagram complementary offset binary 1 offset binary 0 complementary two?s complement 1 (using msb, pin 29) two?s complement 0 (using msb, pin 29) straight binary 1 complimentary binary 0 output format pin 35 logic level table 2a. setting output coding selection (pin 35) ads-931 20k w 33 32 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 overflow eoc bit 1 (msb) bit 1 (msb) bit2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 bit 16 (lsb) analog ground digital ground 0.1f 4.7f 0.1f comp. bits 4.7f +3.2v ref. out fifo read 31 7, 30 35 1 9 +5v digital ?5v +5v offset adjust gain adjust 5 6 3 0.1f 4.7f 4, 36 37 0.1f 4.7f 38 + + 20k w ?5v +5v ?5v +5v analog 12 start convert analog input 34 enable 8 fifo/dir 10 fstat1 11 fstat2 +5v +5v +5v ?5v unipolar connect for unipolar mode 2 6.8f
ads-931 ? ? 6 thermal requirements all datel sampling a/d converters are fully characterized and specified over operating temperature (case) ranges of 0 to +70c and ?55 to +125c. all room-temperature (t a = +25c) production testing is performed without the use of heat sinks or forced-air cooling. thermal impedance figures for each device are listed in their respective specification tables. these devices do not normally require heat sinks, however, standard precautionary design and layout procedures should be used to ensure devices do not overheat. the ground and power planes beneath the package, as well as all pcb signal runs to and from the device, should be as heavy as possible to help conduct heat away from the package. electrically insulating, thermally-conductive "pads" may be installed underneath the package. devices should be soldered to boards rather than "socketed", and of course, minimal air flow over the surface can greatly help reduce the package temperature. in more severe ambient conditions, the package/junction temperature of a given device can be reduced dramatically (typically 35%) by using one of datel's hs series heat sinks. see ordering information for the assigned part number. see page 1-183 of the datel data acquisition components catalog for more information on the hs series. request datel application note an-8, "heat sinks for dip data converters," or contact datel directly, for additional information. figure 4. fft analysis of ads-931 figure 3. ads-931 timing diagram 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 0 50 100 150 200 250 300 350 400 450 500 frequency (khz) (fs = 1mhz, fin = 480khz, vin = ?0.5db, 16,384-point fft) a m p l i t u d e r e l a t i v e t o f u l l s c a l e ( d b ) this device has three pipeline delays. four start convert pulses (clock cycles) must be applied for valid data from the first conversion to appear at the output of the a/d. start convert internal s/h n n+1 acquisition time 730ns typ. 20ns typ. eoc 60ns typ. output data data n-4 valid data n-2 valid invalid data data n-3 valid 20ns typ. n+2 data n-1 valid 940ns typ. 60ns typ. invalid data notes: 100ns typ. n+3 55ns typ. 280ns typ. conversion time hold t he start convert positive pulse width must be between either 40 and 175nsec or 280 and 460nsec (when sampling at 1mhz) to ensure proper operation. for sampling rates lower than 1mhz, the start pulse can be wider than 460nsec, however a minimum pulse width low of 40nsec should be maintained. a 1mhz clock with a 100nsec positive pulse width is used for all production testing. scale is approximately 50ns per division. fs = 1mhz. 1. 2. 3. 270ns typ.
ads-931 ? ? 7 figure 5. ads-931 evaluation board schematic. 20k r4 1 2 3 u2 9 8 7 6 5 4 3 2 11 1 19 18 17 16 15 14 13 12 10 20 74h c t573 uut b6 b7 b8 b9 b10 b11 +5vd dgnd msb msb b2 b3 b4 b5 b12 b13 b14 b15 ls b startco n fstat2 fstat1 nc nc +5va ?5v a ag nd com p enable of eo c read fifo /d ir dgnd gain o ffset ag nd ana in 2 +3.2vref u6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 u1 12 11 13 8 9 10 74h c t74 2.2f c13 1 2 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 p1 fst2 startco fst1 b16 fif/d ir b15 read b14 nc b13 com plim b12 enable b11 dgnd b10 dgnd b9 dgnd b8 dgnd b7 dgnd b6 dgnd b5 dgnd b4 eo c b3 ovrflw b2 b1b b1(m sb) 2.2f c11 1 2 .1 f c20 1 2 u4 9 8 7 6 5 4 3 2 11 1 19 18 17 16 15 14 13 12 10 20 74h c t573 .1 f c15 1 2 33pf c10 1 2 .1 f c18 1 2 .1 f c3 1 2 2.2f c1 1 2 2.2f c14 1 2 2.2f c2 1 2 2.2f c9 1 2 sg 8 sg 7 2.2f c12 1 2 2.2f c21 1 2 r2 1 2 r1 1 2 3.3k r3 1 2 u1 2 3 1 6 5 4 74h c t74 sg 9 1 2 2.2f c22 2.2f c4 1 2 20h l4 1 2 + ? ar1 2 3 4 6 7 .1uf c5 1 2 20h l3 1 2 u3 9 8 7 6 5 4 3 2 11 1 19 18 17 16 15 14 13 12 10 20 74h c t573 sg 4 1 2 sg 3 1 2 x1 1 78 14 1m h z sg 2 1 2 20k r5 1 2 3 74hc86 1 2 3 c6 1 2 2.2f 20h l2 1 2 .1 f c19 1 2 + ? ar2 2 3 4 6 7 op07 j5 p2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 50 r6 1 2 sg 5 1 2 74hc86 12 13 11 74hc86 u5 4 5 6 j2 20h l1 1 2 74hc86 9 10 8 b2 1 2 j3 .1 f c16 1 2 .1 f c17 1 2 2.2f c7 1 2 b1 1 2 j4 j1 .1 f c8 1 2 sg 1 1 2 b3 com p com p enable enable +5va +5va +5va +5va +5va +5va +5va +5va +5vf +5vf +5vf +5vf +5vf +5vf +5vf +5vf +5vf fif fif rd rd startco nv b2 ab9 ab9 +15v +15v +15v eo c eo c of ab8 ab8 ab1 ab1 ab2 ab2 ab3 ab3 ab4 ab4 ab5 ab5 ab6 ab6 ab7 ab7 ab16 ab16 ab15 ab15 ab14 ab14 ab13 ab13 ab12 ab12 ab11 ab11 ab10 ab10 ab10 fifo /d ir read com plim fst1 b15 b14 fst2 ovrflw b1 +5vd +5vd +5vd +5vd +5vd +5vd b4 b5 b6 b7 b1b b13 b16 b8 b12 b11 b10 b9 ?15v ?15v ?15v ag nd ag nd ag nd ag nd ag nd ag nd ag nd ag nd ag nd ag nd ag nd ag nd ag nd ag nd ?5v a -5 v a -5 v a ?5v a ?5v a -5 v a -5 v a -5 v a dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd start co nvert analo g input option am plifier n.c. 3 3 2 2 1 1 7 14 7 (l s b ) gain adj o ffset adj 3 3 3 3 2 2 2 2 1 1 1 1 (m s b ) (m s b ) (l s b ) (m s b ) 14 nv u5 u5 u5
ads-931 ? ? 8 complementary offset binary 1 offset binary 0 complementary two?s complement 1 (using msb, pin 29) two?s complement 0 (using msb, pin 29) straight binary 1 complimentary binary 0 output format pin 35 logic level table 2a. setting output coding selection (pin 35) table 2b. output coding 1111 1111 1111 1111 lsb "1" to "0" 1110 0000 0000 0000 1100 0000 0000 0000 1000 0000 0000 0000 0111 1111 1111 1111 0100 0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 0001 lsb "0" to "1" 0000 0000 0000 0000 msb lsb msb lsb +fs ?1 lsb +fs ?1 1/2 lsb +3/4 fs +1/2 fs 0 ?1 lsb ?1/2 fs ?3/4 fs ?fs +1 lsb ?fs + 1/2 lsb ?fs straight binary input range 2.75v +2.749916 +2.749874 +2.062500 +1.375000 0.000000 ?0.000084 ?1.375000 ?2.062500 ?2.749916 ?2.749958 ?2.750000 0000 0000 0000 0000 lsb "0" to "1" 0001 1111 1111 1111 0011 1111 1111 1111 0111 1111 1111 1111 1000 000 000 0000 1011 1111 1111 1111 1101 1111 1111 1111 1111 1111 1111 1110 lsb "1" to "0" 1111 1111 1111 1111 0111 1111 1111 1111 lsb "1" to "0" 0110 0000 0000 0000 0100 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1100 0000 0000 0000 1010 0000 0000 0000 1000 0000 0000 0001 lsb "0" to "1" 1000 0000 0000 0000 1000 0000 0000 0000 lsb "0" to "1" 1001 1111 1111 1111 1011 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0011 1111 1111 1111 0101 1111 1111 1111 0111 1111 1111 1110 lsb "1" to "0" 0111 1111 1111 1111 bipolar scale input range 0 to ?5.5v unipolar scale ?5.499916 ?5.499874 ?4.812500 ?4.125000 ?2.750000 ?2.749958 ?1.375000 ?0.687500 ?0.000084 ?0.000042 0.000000 ?fs+1 lsb ?fs +1 1/2 lsb ?7/8 fs ?3/4 fs ?1/2 fs ?1/2fs?1/2lsb ?1/4 fs ?1/8 fs ?1 lsb ?1/2 lsb 0 msb lsb msb lsb output coding comp. binary comp. off. bin. offset binary two's comp. comp. two's comp. 0 to ?5.5v pin 3 pin 1 to pin 2 2.75v pin 3 pin 2 is no connect input range input pin connect table 3. input connections
ads-931 ? ? 9 0 2147 0.00 0.71 ?0.56 65,536 65,536 0 figure 5. ads-931 histogram and differential nonlinearity d n l ( l s b ' s ) codes digital output code n u m b e r o f o c c u r r e n c e s figure 6. ads-931 grounded input histogram this histogram represents the typical peak-to-peak noise (including quantization noise) associated with the ads-931. digital output code 0 1000 2000 3000 4000 4530
ads-931 ? ? ? ? innov a tion and ex cellence datel makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. the descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. specifications are subject to change without notice. the datel logo is a registered datel, inc. trademark. ds-0307 9/97 mechanical dimensions inches (mm) ordering information operating model temp. range ads-931mc 0 to +70c ADS-931MM ?55 to +125c receptacles for pc board mounting can be ordered through amp, inc., part # 3-331272-8 (component lead socket), 40 required. for mil-std-883 product, or surface mount packaging, contact datel. accessories ads-b931 evaluation board (without ads-931) hs-40 heat sink for all ads-931 models pin 1 index ( on top) 2.12/2.07 (53.85/52.58) 0.018 0.002 (0.457) 0.100 typ. (2.540) 0.110/0.090 (2.794/2.286) seating plane 0.035/0.015 (0.889/0.381) 0.200/0.175 (5.080/4.445) 0.245 max. (6.223) 0.210 max. (5.334) 0.045/0.035 (1.143/0.889) 1.11/1.08 (28.20/27.43) 1 20 21 40 1.900 0.008 (48.260) dimension tolerances (unless otherwise indicated): 2 place decimal (.xx) 0.010 (0.254) 3 place decimal (.xxx) 0.005 (0.127) lead material: kovar alloy lead finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating 0.015/0.009 (0.381/0.229) 0.900 0.010 (22.86) 0.110/0.090 (2.794/2.286 iso 9001 iso 9001 registered datel, inc. 11 cabot boulevard, mansfield, ma 02048-1151 tel: (508) 339-3000 (800) 233-2765 fax: (508) 339-6356 internet: www.datel.com e-mail:sales@datel.com data sheet fax back: (508) 261-2857 datel (uk) ltd. tadley, england tel: (01256)-880444 datel s.a.r.l. montigny le bretonneux, france tel: 1-34-60-01-01 datel gmbh mnchen, germany tel: 89-544334-0 datel kk tokyo, japan tel: 3-3779-1031, osaka tel: 6-354-2025
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